"Merge Tagged PR 10008"

src/audio_core/sink/sink_stream.cpp

@@ -252,8 +252,7 @@ void SinkStream::ProcessAudioOutAndRender(std::span<s16> output_buffer, std::siz
 
     {
         std::scoped_lock lk{sample_count_lock};
-        last_sample_count_update_time =
-            Core::Timing::CyclesToUs(system.CoreTiming().GetClockTicks());
+        last_sample_count_update_time = system.CoreTiming().GetGlobalTimeNs();
         min_played_sample_count = max_played_sample_count;
         max_played_sample_count += actual_frames_written;
     }
@@ -261,12 +260,13 @@ void SinkStream::ProcessAudioOutAndRender(std::span<s16> output_buffer, std::siz
 
 u64 SinkStream::GetExpectedPlayedSampleCount() {
     std::scoped_lock lk{sample_count_lock};
-    auto cur_time{Core::Timing::CyclesToUs(system.CoreTiming().GetClockTicks())};
+    auto cur_time{system.CoreTiming().GetGlobalTimeNs()};
     auto time_delta{cur_time - last_sample_count_update_time};
     auto exp_played_sample_count{min_played_sample_count +
                                  (TargetSampleRate * time_delta) / std::chrono::seconds{1}};
 
-    return std::min<u64>(exp_played_sample_count, max_played_sample_count);
+    // Add 15ms of latency in sample reporting to allow for some leeway in scheduler timings
+    return std::min<u64>(exp_played_sample_count, max_played_sample_count) + TargetSampleCount * 3;
 }
 
 void SinkStream::WaitFreeSpace() {

src/audio_core/sink/sink_stream.h

@@ -246,7 +246,7 @@ private:
     /// Maximum number of total samples that can be played since the last callback
     u64 max_played_sample_count{};
     /// The time the two above tracking variables were last written to
-    std::chrono::microseconds last_sample_count_update_time{};
+    std::chrono::nanoseconds last_sample_count_update_time{};
     /// Set by the audio render/in/out system which uses this stream
     f32 system_volume{1.0f};
     /// Set via IAudioDevice service calls

src/shader_recompiler/backend/glsl/emit_glsl_image.cpp

@@ -143,6 +143,21 @@ IR::Inst* PrepareSparse(IR::Inst& inst) {
     }
     return sparse_inst;
 }
+
+std::string ImageGatherSubpixelOffset(const IR::TextureInstInfo& info, std::string_view texture,
+                                      std::string_view coords) {
+    switch (info.type) {
+    case TextureType::Color2D:
+    case TextureType::Color2DRect:
+        return fmt::format("{}+vec2(0.001953125)/vec2(textureSize({}, 0))", coords, texture);
+    case TextureType::ColorArray2D:
+    case TextureType::ColorCube:
+        return fmt::format("vec3({0}.xy+vec2(0.001953125)/vec2(textureSize({1}, 0)),{0}.z)", coords,
+                           texture);
+    default:
+        return std::string{coords};
+    }
+}
 } // Anonymous namespace
 
 void EmitImageSampleImplicitLod(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
@@ -340,6 +355,13 @@ void EmitImageGather(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
         LOG_WARNING(Shader_GLSL, "Device does not support sparse texture queries. STUBBING");
         ctx.AddU1("{}=true;", *sparse_inst);
     }
+    std::string coords_with_subpixel_offset;
+    if (ctx.profile.need_gather_subpixel_offset) {
+        // Apply a subpixel offset of 1/512 the texel size of the texture to ensure same rounding on
+        // AMD hardware as on Maxwell or other Nvidia architectures.
+        coords_with_subpixel_offset = ImageGatherSubpixelOffset(info, texture, coords);
+        coords = coords_with_subpixel_offset;
+    }
     if (!sparse_inst || !supports_sparse) {
         if (offset.IsEmpty()) {
             ctx.Add("{}=textureGather({},{},int({}));", texel, texture, coords,
@@ -387,6 +409,13 @@ void EmitImageGatherDref(EmitContext& ctx, IR::Inst& inst, const IR::Value& inde
         LOG_WARNING(Shader_GLSL, "Device does not support sparse texture queries. STUBBING");
         ctx.AddU1("{}=true;", *sparse_inst);
     }
+    std::string coords_with_subpixel_offset;
+    if (ctx.profile.need_gather_subpixel_offset) {
+        // Apply a subpixel offset of 1/512 the texel size of the texture to ensure same rounding on
+        // AMD hardware as on Maxwell or other Nvidia architectures.
+        coords_with_subpixel_offset = ImageGatherSubpixelOffset(info, texture, coords);
+        coords = coords_with_subpixel_offset;
+    }
     if (!sparse_inst || !supports_sparse) {
         if (offset.IsEmpty()) {
             ctx.Add("{}=textureGather({},{},{});", texel, texture, coords, dref);

src/shader_recompiler/backend/spirv/emit_spirv_image.cpp

@@ -261,6 +261,30 @@ Id BitTest(EmitContext& ctx, Id mask, Id bit) {
     const Id bit_value{ctx.OpBitwiseAnd(ctx.U32[1], shifted, ctx.Const(1u))};
     return ctx.OpINotEqual(ctx.U1, bit_value, ctx.u32_zero_value);
 }
+
+Id ImageGatherSubpixelOffset(EmitContext& ctx, const IR::TextureInstInfo& info, Id texture,
+                             Id coords) {
+    // Apply a subpixel offset of 1/512 the texel size of the texture to ensure same rounding on
+    // AMD hardware as on Maxwell or other Nvidia architectures.
+    const auto calculate_coords{[&](size_t dim) {
+        const Id nudge{ctx.Const(0x1p-9f)};
+        const Id image_size{ctx.OpImageQuerySizeLod(ctx.U32[dim], texture, ctx.u32_zero_value)};
+        Id offset{dim == 2 ? ctx.ConstantComposite(ctx.F32[dim], nudge, nudge)
+                           : ctx.ConstantComposite(ctx.F32[dim], nudge, nudge, ctx.f32_zero_value)};
+        offset = ctx.OpFDiv(ctx.F32[dim], offset, ctx.OpConvertUToF(ctx.F32[dim], image_size));
+        return ctx.OpFAdd(ctx.F32[dim], coords, offset);
+    }};
+    switch (info.type) {
+    case TextureType::Color2D:
+    case TextureType::Color2DRect:
+        return calculate_coords(2);
+    case TextureType::ColorArray2D:
+    case TextureType::ColorCube:
+        return calculate_coords(3);
+    default:
+        return coords;
+    }
+}
 } // Anonymous namespace
 
 Id EmitBindlessImageSampleImplicitLod(EmitContext&) {
@@ -423,6 +447,9 @@ Id EmitImageGather(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id
                    const IR::Value& offset, const IR::Value& offset2) {
     const auto info{inst->Flags<IR::TextureInstInfo>()};
     const ImageOperands operands(ctx, offset, offset2);
+    if (ctx.profile.need_gather_subpixel_offset) {
+        coords = ImageGatherSubpixelOffset(ctx, info, TextureImage(ctx, info, index), coords);
+    }
     return Emit(&EmitContext::OpImageSparseGather, &EmitContext::OpImageGather, ctx, inst,
                 ctx.F32[4], Texture(ctx, info, index), coords, ctx.Const(info.gather_component),
                 operands.MaskOptional(), operands.Span());
@@ -432,6 +459,9 @@ Id EmitImageGatherDref(EmitContext& ctx, IR::Inst* inst, const IR::Value& index,
                        const IR::Value& offset, const IR::Value& offset2, Id dref) {
     const auto info{inst->Flags<IR::TextureInstInfo>()};
     const ImageOperands operands(ctx, offset, offset2);
+    if (ctx.profile.need_gather_subpixel_offset) {
+        coords = ImageGatherSubpixelOffset(ctx, info, TextureImage(ctx, info, index), coords);
+    }
     return Emit(&EmitContext::OpImageSparseDrefGather, &EmitContext::OpImageDrefGather, ctx, inst,
                 ctx.F32[4], Texture(ctx, info, index), coords, dref, operands.MaskOptional(),
                 operands.Span());

src/shader_recompiler/profile.h

@@ -52,6 +52,10 @@ struct Profile {
     bool need_declared_frag_colors{};
     /// Prevents fast math optimizations that may cause inaccuracies
     bool need_fastmath_off{};
+    /// Some GPU vendors use a different rounding precision when calculating texture pixel
+    /// coordinates with the 16.8 format in the ImageGather instruction than the Maxwell
+    /// architecture. Applying an offset does fix this mismatching rounding behaviour.
+    bool need_gather_subpixel_offset{};
 
     /// OpFClamp is broken and OpFMax + OpFMin should be used instead
     bool has_broken_spirv_clamp{};

src/video_core/engines/maxwell_3d.h

@@ -856,8 +856,8 @@ public:
 
         struct ZetaSize {
             enum class DimensionControl : u32 {
-                DepthDefinesArray = 0,
-                ArraySizeOne = 1,
+                DefineArraySize = 0,
+                ArraySizeIsOne = 1,
             };
 
             u32 width;
@@ -1104,8 +1104,8 @@ public:
 
         struct TileMode {
             enum class DimensionControl : u32 {
-                DepthDefinesArray = 0,
-                DepthDefinesDepth = 1,
+                DefineArraySize = 0,
+                DefineDepthSize = 1,
             };
             union {
                 BitField<0, 4, u32> block_width;

src/video_core/renderer_opengl/gl_device.h

@@ -176,6 +176,10 @@ public:
         return vendor_name == "ATI Technologies Inc.";
     }
 
+    bool IsIntel() const {
+        return vendor_name == "Intel";
+    }
+
     bool CanReportMemoryUsage() const {
         return can_report_memory;
     }

src/video_core/renderer_opengl/gl_shader_cache.cpp

@@ -218,6 +218,7 @@ ShaderCache::ShaderCache(RasterizerOpenGL& rasterizer_, Core::Frontend::EmuWindo
           .lower_left_origin_mode = true,
           .need_declared_frag_colors = true,
           .need_fastmath_off = device.NeedsFastmathOff(),
+          .need_gather_subpixel_offset = device.IsAmd() || device.IsIntel(),
 
           .has_broken_spirv_clamp = true,
           .has_broken_unsigned_image_offsets = true,

src/video_core/renderer_vulkan/vk_pipeline_cache.cpp

@@ -329,6 +329,9 @@ PipelineCache::PipelineCache(RasterizerVulkan& rasterizer_, const Device& device
 
         .lower_left_origin_mode = false,
         .need_declared_frag_colors = false,
+        .need_gather_subpixel_offset = driver_id == VK_DRIVER_ID_AMD_PROPRIETARY ||
+                                       driver_id == VK_DRIVER_ID_INTEL_PROPRIETARY_WINDOWS ||
+                                       driver_id == VK_DRIVER_ID_INTEL_OPEN_SOURCE_MESA,
 
         .has_broken_spirv_clamp = driver_id == VK_DRIVER_ID_INTEL_PROPRIETARY_WINDOWS,
         .has_broken_spirv_position_input = driver_id == VK_DRIVER_ID_QUALCOMM_PROPRIETARY,

src/video_core/texture_cache/image_info.cpp

@@ -14,6 +14,7 @@
 
 namespace VideoCommon {
 
+using Tegra::Engines::Fermi2D;
 using Tegra::Engines::Maxwell3D;
 using Tegra::Texture::TextureType;
 using Tegra::Texture::TICEntry;
@@ -114,86 +115,89 @@ ImageInfo::ImageInfo(const TICEntry& config) noexcept {
     }
 }
 
-ImageInfo::ImageInfo(const Maxwell3D::Regs& regs, size_t index) noexcept {
-    const auto& rt = regs.rt[index];
-    format = VideoCore::Surface::PixelFormatFromRenderTargetFormat(rt.format);
+ImageInfo::ImageInfo(const Maxwell3D::Regs::RenderTargetConfig& ct,
+                     Tegra::Texture::MsaaMode msaa_mode) noexcept {
+    format = VideoCore::Surface::PixelFormatFromRenderTargetFormat(ct.format);
     rescaleable = false;
-    if (rt.tile_mode.is_pitch_linear) {
-        ASSERT(rt.tile_mode.dim_control ==
-               Maxwell3D::Regs::TileMode::DimensionControl::DepthDefinesArray);
+    if (ct.tile_mode.is_pitch_linear) {
+        ASSERT(ct.tile_mode.dim_control ==
+               Maxwell3D::Regs::TileMode::DimensionControl::DefineArraySize);
         type = ImageType::Linear;
-        pitch = rt.width;
+        pitch = ct.width;
         size = Extent3D{
             .width = pitch / BytesPerBlock(format),
-            .height = rt.height,
+            .height = ct.height,
             .depth = 1,
         };
         return;
     }
-    size.width = rt.width;
-    size.height = rt.height;
-    layer_stride = rt.array_pitch * 4;
+    size.width = ct.width;
+    size.height = ct.height;
+    layer_stride = ct.array_pitch * 4;
     maybe_unaligned_layer_stride = layer_stride;
-    num_samples = NumSamples(regs.anti_alias_samples_mode);
+    num_samples = NumSamples(msaa_mode);
     block = Extent3D{
-        .width = rt.tile_mode.block_width,
-        .height = rt.tile_mode.block_height,
-        .depth = rt.tile_mode.block_depth,
+        .width = ct.tile_mode.block_width,
+        .height = ct.tile_mode.block_height,
+        .depth = ct.tile_mode.block_depth,
     };
-    if (rt.tile_mode.dim_control ==
-        Maxwell3D::Regs::TileMode::DimensionControl::DepthDefinesDepth) {
+    if (ct.tile_mode.dim_control == Maxwell3D::Regs::TileMode::DimensionControl::DefineDepthSize) {
         type = ImageType::e3D;
-        size.depth = rt.depth;
+        size.depth = ct.depth;
     } else {
         rescaleable = block.depth == 0;
         rescaleable &= size.height > 256;
         downscaleable = size.height > 512;
         type = ImageType::e2D;
-        resources.layers = rt.depth;
+        resources.layers = ct.depth;
     }
 }
 
-ImageInfo::ImageInfo(const Tegra::Engines::Maxwell3D::Regs& regs) noexcept {
-    format = VideoCore::Surface::PixelFormatFromDepthFormat(regs.zeta.format);
-    size.width = regs.zeta_size.width;
-    size.height = regs.zeta_size.height;
+ImageInfo::ImageInfo(const Maxwell3D::Regs::Zeta& zt, const Maxwell3D::Regs::ZetaSize& zt_size,
+                     Tegra::Texture::MsaaMode msaa_mode) noexcept {
+    format = VideoCore::Surface::PixelFormatFromDepthFormat(zt.format);
+    size.width = zt_size.width;
+    size.height = zt_size.height;
     rescaleable = false;
     resources.levels = 1;
-    layer_stride = regs.zeta.array_pitch * 4;
+    layer_stride = zt.array_pitch * 4;
     maybe_unaligned_layer_stride = layer_stride;
-    num_samples = NumSamples(regs.anti_alias_samples_mode);
+    num_samples = NumSamples(msaa_mode);
     block = Extent3D{
-        .width = regs.zeta.tile_mode.block_width,
-        .height = regs.zeta.tile_mode.block_height,
-        .depth = regs.zeta.tile_mode.block_depth,
+        .width = zt.tile_mode.block_width,
+        .height = zt.tile_mode.block_height,
+        .depth = zt.tile_mode.block_depth,
     };
-    if (regs.zeta.tile_mode.is_pitch_linear) {
-        ASSERT(regs.zeta.tile_mode.dim_control ==
-               Maxwell3D::Regs::TileMode::DimensionControl::DepthDefinesArray);
+    if (zt.tile_mode.is_pitch_linear) {
+        ASSERT(zt.tile_mode.dim_control ==
+               Maxwell3D::Regs::TileMode::DimensionControl::DefineArraySize);
         type = ImageType::Linear;
         pitch = size.width * BytesPerBlock(format);
-    } else if (regs.zeta.tile_mode.dim_control ==
-               Maxwell3D::Regs::TileMode::DimensionControl::DepthDefinesDepth) {
-        ASSERT(regs.zeta.tile_mode.is_pitch_linear == 0);
-        ASSERT(regs.zeta_size.dim_control ==
-               Maxwell3D::Regs::ZetaSize::DimensionControl::ArraySizeOne);
+    } else if (zt.tile_mode.dim_control ==
+               Maxwell3D::Regs::TileMode::DimensionControl::DefineDepthSize) {
+        ASSERT(zt_size.dim_control == Maxwell3D::Regs::ZetaSize::DimensionControl::ArraySizeIsOne);
         type = ImageType::e3D;
-        size.depth = regs.zeta_size.depth;
+        size.depth = zt_size.depth;
     } else {
-        ASSERT(regs.zeta_size.dim_control ==
-               Maxwell3D::Regs::ZetaSize::DimensionControl::DepthDefinesArray);
         rescaleable = block.depth == 0;
         downscaleable = size.height > 512;
         type = ImageType::e2D;
-        resources.layers = regs.zeta_size.depth;
+        switch (zt_size.dim_control) {
+        case Maxwell3D::Regs::ZetaSize::DimensionControl::DefineArraySize:
+            resources.layers = zt_size.depth;
+            break;
+        case Maxwell3D::Regs::ZetaSize::DimensionControl::ArraySizeIsOne:
+            resources.layers = 1;
+            break;
+        }
     }
 }
 
-ImageInfo::ImageInfo(const Tegra::Engines::Fermi2D::Surface& config) noexcept {
+ImageInfo::ImageInfo(const Fermi2D::Surface& config) noexcept {
     UNIMPLEMENTED_IF_MSG(config.layer != 0, "Surface layer is not zero");
     format = VideoCore::Surface::PixelFormatFromRenderTargetFormat(config.format);
     rescaleable = false;
-    if (config.linear == Tegra::Engines::Fermi2D::MemoryLayout::Pitch) {
+    if (config.linear == Fermi2D::MemoryLayout::Pitch) {
         type = ImageType::Linear;
         size = Extent3D{
             .width = config.pitch / VideoCore::Surface::BytesPerBlock(format),

src/video_core/texture_cache/image_info.h

@@ -17,8 +17,11 @@ using VideoCore::Surface::PixelFormat;
 struct ImageInfo {
     ImageInfo() = default;
     explicit ImageInfo(const TICEntry& config) noexcept;
-    explicit ImageInfo(const Tegra::Engines::Maxwell3D::Regs& regs, size_t index) noexcept;
-    explicit ImageInfo(const Tegra::Engines::Maxwell3D::Regs& regs) noexcept;
+    explicit ImageInfo(const Tegra::Engines::Maxwell3D::Regs::RenderTargetConfig& ct,
+                       Tegra::Texture::MsaaMode msaa_mode) noexcept;
+    explicit ImageInfo(const Tegra::Engines::Maxwell3D::Regs::Zeta& zt,
+                       const Tegra::Engines::Maxwell3D::Regs::ZetaSize& zt_size,
+                       Tegra::Texture::MsaaMode msaa_mode) noexcept;
     explicit ImageInfo(const Tegra::Engines::Fermi2D::Surface& config) noexcept;
     explicit ImageInfo(const Tegra::DMA::ImageOperand& config) noexcept;
 

src/video_core/texture_cache/texture_cache.h

@@ -1503,7 +1503,7 @@ ImageViewId TextureCache<P>::FindColorBuffer(size_t index, bool is_clear) {
     if (rt.format == Tegra::RenderTargetFormat::NONE) {
         return ImageViewId{};
     }
-    const ImageInfo info(regs, index);
+    const ImageInfo info(regs.rt[index], regs.anti_alias_samples_mode);
     return FindRenderTargetView(info, gpu_addr, is_clear);
 }
 
@@ -1517,7 +1517,7 @@ ImageViewId TextureCache<P>::FindDepthBuffer(bool is_clear) {
     if (gpu_addr == 0) {
         return ImageViewId{};
     }
-    const ImageInfo info(regs);
+    const ImageInfo info(regs.zeta, regs.zeta_size, regs.anti_alias_samples_mode);
     return FindRenderTargetView(info, gpu_addr, is_clear);
 }